High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof

ABSTRACT

A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

RELATED APPLICATIONS

[0001] This application is cross referenced to U.S. patent applicationSer. No. ______ (Attorney docket YOR920010723US1) by Q. Ouyang and Jack0. Chu, the inventors herein, filed herewith, entitled “Low LeakageHeterojunction Vertical Transistors and High Performance DevicesThereof” which is directed to a vertical p-channel MOSFET which isincorporated herein by reference and assigned to the assignee herein.

[0002] This application is further cross referenced to U.S. patentapplication Ser. No. ______ (Attorney docket YOR920030140US1) by Q.Ouyang and Jack O. Chu, the inventors herein, filed herewith, entitled“Ultra Scalable High Speed Heterojunction Vertical n-channel MISFETs andMethods Thereof” which is directed to vertical n-channel MISFETs whichis incorporated herein by reference and assigned to the assignee herein.

FIELD OF THE INVENTION

[0003] This invention relates to semiconductor transistors and, moreparticularly, to a metal insulator semiconductor field effect transistor(MISFET) consisting of a conducting channel which has no hetero-barrierin the current flow direction and a heterojunction between thesource/drain and body (bulk) of the transistor.

BACKGROUND OF THE INVENTION

[0004] Silicon MOSFET scaling has become a major challenge in thesemiconductor industry. Traditional techniques start to fail in reducingcertain undesirable physical effects as device dimensions shrink down tothe nanometer regime. For example, anti-punchthrough (APT) or haloimplantation is used to reduce the short-channel effects (SCE). However,the abrupt doping profiles are difficult to achieve due to temperatureenhanced diffusion, and these highly doped channels or pocket implantregions increase junction capacitance and band-to-band tunneling. It hasbeen shown by S. Thompson, et al., in “MOS scaling: transistorchallenges for the 21st century,” Intel Technology Journal, Q3, 1998,that channel engineering can only decrease the circuit gate delay by˜10% for a given technology, and it cannot provide channel lengthscaling for generation after generation that gate oxide and source/drain(S/D) junction depth scaling has provided.

[0005] With bandgap engineering, an important degree of freedom can beprovided in the device design. The growth of high-quality tensilestrained Si/SiGe and compressively strained SiGe/Si heterostructures bymolecular beam epitaxy (MBE), various types of chemical vapor deposition(CVD), and/or ion implantation allows incorporation of bandgapengineering concepts into a mature silicon technology.

[0006] Bandgap engineering has been utilized to realize various types ofheterojunction field effect transistors (HFETs). The most widely studiedis the modulation doped field effect transistors (MODFETs), in which aquantum well is used to confine the carriers in a lightly dopedsemiconductor (See K. Ismail, “Si/SiGe High-Speed Field-EffectTransistors”, IEDM, Tech. Dig., p. 509-512, 1995). Higher carriermobility can be achieved due to reduced impurity scattering, reducedsurface roughness scattering in the buried channel, and strained-inducedmobility enhancement, if any, depending on the hetero material systememployed. Derived from the same concept, various types ofheterostructure CMOS devices have also been proposed and studied (See M.A. Armstong, et al., “Design of Si/SiGe Heterojunction ComplementaryMetal-Oxide Semiconductor Transistors”, IEDM Tech. Dig., p. 761-764,1995; S. Imai et al., “Si—SiGe Semiconductor Device and Method ofFabricating the Same”, U.S. Pat. No. 5,847,419; and M. Kubo, et al.,“Method of Forming HCMOS Devices with a Silicon-Germanium-Carboncompound Semiconductor Layer”, U.S. Pat. No. 6,190,975, Feb. 20, 2001.)The advantage of these devices is the higher carrier mobility and hencehigh drive current and high speed. However, two prominent problemsremain in these planar devices: device scaling and control ofshort-channel effects.

[0007] As for short-channel effects, other than ultra-steep retrogradedchannel profiles and ultra-shallow source/drain junctions,silicon-on-insulator (SOI) has been used to control short-channeleffects. However, SOI alone cannot remove the short-channel effectscompletely, and moreover, an inherent problem with SOI is the floatingbody effect. Another way to reduce the short-channel effect is to have abuilt-in energy barrier at the source/body junction, and in particular abarrier where the barrier height does not depend on the applied bias.The band offset provided by a heterojunction is very suitable in thiscase. A heterojunction MOSFET (HJMOSFET) was been proposed and studiedby S. Hareland, et al., in “New structural approach for reducingpunchthrough current in deep submicrometer MOSFETs and extending MOSFETscaling,” IEEE Electronics Letters, vol. 29, no. 21, pp. 1894-1896,October 1993, and by X. D. Chen, et al., in “Vertical P-MOSFETS withheterojunction between source/drain and channel,” Device ResearchConference, Denver, June 2000.

[0008] Recently, a lateral, high mobility, p-channel heterojunctiontransistor (HMHJT) has been proposed by Q. Ouyang, et al., in U.S. Pat.No. 6,319,799. A detailed simulation study has been performed by Q.Ouyang, et al., in “A Novel Si/SiGe Heterojunction pMOSFET with ReducedShort-Channel Effects and Enhanced Drive Current,” IEEE Transactions onElectron Devices, 47 (10), 2000. In order to achieve complementaryMISFETs using such a pMISFET, a comparable high performance nMISFET isneeded. In the present invention, a lateral, high performance,heterojunction nMISFET is proposed and two embodiments are illustrated.Two embodiments for the complementary MOSFET are presented. The methodsthereof are also described.

[0009] U.S. Pat. No. 5,285,088 describes a “High Electron MobilityTransistor”. This device has a pair of semiconductor layers forsource/drain electrodes consisting of a poly SiGe layer and a poly Silayer so as to form a partially projected “overhanging-shape” over theactive area. In this case, the source/drain and the gate areself-aligned. However, it is a planar structure and still suffers fromthe short-channel effects.

SUMMARY OF THE INVENTION

[0010] The objective of this invention is to provide a device structurethat has superb performance and scalability. By using 2-dimensionalbandgap engineering, the tradeoffs in the conventional Si technology canbe avoided, and the drive current and leakage current can be optimizedindependently. Consequently, very high drive current and excellentturn-off characteristics can be achieved simultaneously. Moreover, thesuppression of short-channel effects in such a device further allowscontinuous and more aggressive scaling of the MOSFET technology.

[0011] This invention describes a lateral n-channel and complementaryMISFET structure having these advantages with various embodiments.Another aspect of this invention is the process integration scheme forsuch devices. The devices described in this invention have at least ahetero-barrier between the source and the body of the transistor,however, there is no hetero-barrier in the channel along the currentflow direction. Drain induced barrier lowering is substantially reduceddue to the hetero-barrier at the source junction, hence, thesubsthreshold swing and off-state leakage are reduced. Meanwhile, thedrive current is not limited by quantum mechanical tunneling since thereis no hetero-barrier in the channel. Therefore, with these devices, veryhigh on/off ratio can be achieved. Such devices are superb in highspeed, low leakage and low power applications, such as DRAM, laptopcomputers, and wireless communications.

[0012] Any hetero-material system with the proper band offset may beused to realize the device concept such as silicon-based or Ill-Vmaterial systems. Since silicon technology is the most mature, siliconbased materials are the most economically feasible and attractive. Thereare two types of Si-based heterostructures which have the suitable bandoffset for electrons in nMISFETs. One is tensile strained Si or SiGe onrelaxed SiGe buffer layers, and the other is tensile strainedSi_(1-x-y)Ge_(x)C_(y) on Si. On the other hand, in order to formcomplementary MISFETs, compressively strained SiGe or SiGeC on siliconcan be used for pMISFETs, because it has the suitable band offset forholes. With each material system, the channel could be a surface channelor a buried quantum well channel, and the device can be built on varioussubstrates such as bulk silicon, silicon-on-insulator, SiGe-on-insulatoror silicon-on-sapphire substrate.

[0013] In the present invention, three embodiments for a lateraln-channel transistor are illustrated. Then two embodiments for a lateralCMOS are further described. The fabrication methods are also described.

BRIEF DESCRIPTION OF THE DRAWING

[0014] These and other features, objects, and advantages of the presentinvention will become apparent upon consideration of the followingdetailed description of the invention when read in conjunction with thedrawing in which:

[0015]FIG. 1 is an energy band diagram of compressively strained SiGe orSiGe(C) on cubic Si.

[0016]FIG. 2 is an energy band diagram of tensile strained SiC on cubicSi.

[0017]FIG. 3 is an energy band diagram of tensile strained Si on relaxedSiGe buffer.

[0018]FIG. 4 is a cross sectional schematic of a lateral tensilestrained Si surface channel nMOSFET according to the first embodiment ofthe present invention.

[0019]FIG. 5 is a cross sectional schematic of a lateral surface channelnMOSFET having tensile strained SiC in the source/drain regionsaccording to a second embodiment of the present invention.

[0020]FIG. 6 is a cross sectional schematic of a lateral CMOS withtensile strained SiC source/drain for the nMOSFET and compressivelystrained Si_(1-x-y)Ge_(x)C_(y) source/drain for pMOSFET.

[0021]FIG. 7 is a cross sectional schematic of a lateral CMOS withtensile strained Si_(1-y)C_(y) source/drain for the nMOSFET andcompressively strained Si_(1-x-y)Ge_(x)C_(y) source/drain for pMOSFET.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The lattice spacing of carbon, silicon and germanium are 3.567 Å,5.431 Å and 5.646 Å, respectively. Biaxial tensile strain exists inpseudomorphic SiC on relaxed Si, or in pseudomorphic Si on relaxed SiGeor Ge substrate. Biaxial tensile strain means a larger lattice spacingin the growth plane (surface) and a smaller lattice spacing in thegrowth direction (normal to the surface) in the pseudomorphic material.On the other hand, compressive biaxial strain exists in pseudomorphicSiGe on relaxed Si, in pseudomorphic SiGeC on relaxed Si, or inpseudomorphic Ge on relaxed SiGe. Compressive biaxial strain means asmaller lattice spacing in the growth plane (surface) and a largerlattice spacing in the growth direction (normal to the surface) in thepseudomorphic material. Adding a small amount of carbon (<1%) intocompressively strained SiGe on relaxed Si can compensate and reduce thestrain in SiGe. Strain changes the band structure of the strainedmaterial. Therefore, strain may affect the energy band offset, effectivemass and density of states. Referring to the drawing, FIG. 1 shows theconduction band and valence band of compressively strained SiGe(C) onsilicon by curves 2 and 3, respectively. Holes are confined in thecompressively strained SiGe(C) which has high hole mobility, and thismaterial system is suitable for pMOSFETs.

[0023]FIG. 2 shows the conduction band and valence band of tensilestrained Si_(1-y)C_(y) on relaxed Si buffer layer by curves 4 and 5,respectively. In this case, electrons are confined in the tensilestrained Si_(1-y)C_(y) which potentially has high electron mobility, andthis material system is suitable for nMOSFETs. Furthermore, FIG. 3 showsthe conduction band and valence band of tensile strained silicon onrelaxed silicon germanium by curves 6 and 7, respectively. Electrons areconfined in the tensile strained silicon which has high electronmobility, and this material system is suitable for nMOSFETs. With thethree material systems, the channel could either be a surface channel ora buried quantum well channel. In FIGS. 1-3, the ordinate representsenergy and the abscissa represents depth.

[0024] The cross sectional schematic for the first embodiment of a SiGebased lateral nMOSFET 78 is shown in FIG. 4. The device has thefollowing structural characteristics:

[0025] 1) The drain is n⁺-type tensile strained silicon 82;

[0026] 2) The body is p-type relaxed SiGe 81, and the doping level isadjusted to achieve desirable the threshold voltage;

[0027] 3) The source is n⁺-type tensile strained silicon 83;

[0028] 4) The channel is tensile strained Si 84, and there is nohetero-barrier along the current flow direction shown by arrow 93. Thechannel forms a heterojunction with the body 81 at the interface 805which functions to provide a band offset as shown in FIG. 3 to confineelectrons in the Si channel 84. The channel is typically autodoped bythe layer below. Thus the channel region over the body 81 is autodpedp-type, while the channel region over the source 83 and drain 82 aredoped n-type. There are other ways to provide the desired doping in thechannel layer and source/drain.

[0029] 5) A strained Si/SiGe heterojunction is formed between the sourceand the body at the interface 800, and preferably, aligned with thesource/body metallurgical p/n junction. The heterojunction functions toblock electrons from entering body 81, hence can reduce the off-statecurrent by orders of magnitude. Futhermore, the higher the strain in theheterojunction, the higher the energy barrier becomes and in which casethe leakage current from source to body then to drain can even befurther reduced when the device is turned off.

[0030] 6) A strained Si/SiGe heterojunction is formed between the drainand the body at the interface 810, and preferably, aligned with thedrain/body metallurgical p/n junction;

[0031] 7) The gate is a conducting layer 86 overlapping the entirestrained silicon channel 84 and part of the source 83 and drain 82 withan insulator 85 in between;

[0032] 8) The source, gate and drain electrodes 90, 91, 92 are coupledto the source 83, gate 86, and drain 82, respectively;

[0033] 9) The device isolation is provided by an insulator layer 89;

[0034] 10) Buffer layer 94 provides a relaxed SiGe lattice template forlayer 81. Layer 80 may be bulk silicon, SOI substrate, bulk Ge,Ge-on-insulator, SiGe-on-insulator or silicon-on-sapphire.

[0035] 11) Insulator layer 87 protects the gate stack 85 and 86.

[0036] 12) Insulator layer 88 may be combined with layer 89 as one.

[0037] Besides using a relaxed SiGe as the virtual substrate to generatea tensile strained Si layer, tensile strained SiC on silicon can also beused for nMOSFET. The cross sectional schematic for the secondembodiment of such a silicon-based lateral nMOSFET 112 is shown in FIG.5. The device has the following structural characteristics:

[0038] 1) The drain is n⁺-type tensile strained SiC 32;

[0039] 2) The body is p-type silicon 31, and the doping level isadjusted to achieve the desirable threshold voltage;

[0040] 3) The source is n⁺-type tensile strained SiC 33;

[0041] 4) The channel is silicon or tensile strained SiC 34, and thereis no hetero-barrier along the current flow direction;

[0042] 5) A strained SiC/Si heterojunction is formed between the sourceand the body at the interface 820, and is preferably, aligned with thesource/body metallurgical p/n junction;

[0043] 6) A strained SiC/Si heterojunction is formed between the drainand the body at the interface 830, and is preferably, aligned with thedrain/body metallurgical p/n junction;

[0044] 7) The gate is a conducting layer 36 overlapping the entirechannel 34 and part of the source 33 and drain 32 with an insulator 35in between;

[0045] 8) The source, gate and drain electrodes 40, 41 and 42 arecoupled to the source 33, gate 36, and drain 32, respectively;

[0046] 9) The device isolation is an insulator layer 39.

[0047] 10) Layer 30 may be bulk silicon or a SOI substrate.

[0048] 11) Insulator layer 37 protects the gate stack 35 and 36.

[0049] 12) Insulator layer 38 may be combined with layer 39 as one.

[0050]FIG. 6 shows an embodiment of a lateral CMOS inverter 282, whichis a combination of a lateral symmetric nMOSFET 112 and a lateralsymmetric pMOSFET 280. The device isolation is provided by insulatorregions 39 and 50. The nMOSFET 112 has a tensile strained SiCsource/drain 32, 33 and a silicon or strained SiC channel 34; whereasthe pMOSFET 280 has a compressively strained SiGeC source/drain 132, 133and a silicon or strained SiGeC channel 134. The gate insulator 35 and135 can be oxide, oxynitride, other high-permittivity dielectrics, or acombination thereof. The gate electrode 36, 136 can be the same kind ofmetal with a mid-gap work function, or a n-type poly silicon or polySiGe for nMOSFET and p-type poly silicon or poly SiGe for pMOSFET,respectively.

[0051]FIG. 7 shows a second embodiment for a lateral CMOS inverter 382,which is the same as FIG. 6 except for the nMOSFET 312. In this case,the nMOSFET 312 utilizes a tensile strained silicon source/drain 532,533 and a tensile strained silicon channel 534. The gate insulator 35and 135 can be oxide, oxynitride, other high-permittivity dielectrics,or a combination thereof. The gate electrode 36, 136 can be the samekind of metal with a mid-gap work function, or a n-type poly silicon orpoly SiGe for nMOS and p-type poly silicon or poly SiGe for pMOS,respectively.

[0052] According to the preferred embodiment, this invention furthercomprises the scheme for process integration for a lateralheterojunction nMISFET:

[0053] a) Define a active region and form a well within on silicon,relaxed SiGe bulk, SOI, SGOI or GOI substrate;

[0054] b) Further define and form a gate region with a stack ofdielectrics as a mask preferrably for selective processing;

[0055] c) Etch openings to form the recessed source and drain, which areself-aligned to said gate stack;

[0056] d) Preferably, do a selective epitaxial growth to form thetensile or compressively strained source/drain regions with or withoutin-situ doping;

[0057] e) Removal of said gate stack and planazation if necessary;

[0058] f) Epitaxial growth of the channel layer, plus the cap layer ifdesired for a buried channel device in an uniform manner over the wellregion and the source/drain regions;

[0059] g) Growth or deposition of a gate insulator layer, which may bean oxide, oxinitride, other high-permittivity dielectrics, singly or acombination thereof;

[0060] h) Growth or deposition of a gate electrode layer; which may bepoly silicon, poly SiGe or metal;

[0061] i) Gate patterning and formation;

[0062] j) Ion implanting and annealing if the source, drain are notin-situ doped;

[0063] k) Deposition of field oxide;

[0064] l) Opening for contacts;

[0065] m) Source/drain and gate silicidation;

[0066] n) Metallization and metal sintering.

[0067] It should be noted that in the drawing like elements orcomponents are referred to by like and corresponding reference numerals.

[0068] While there has been described and illustrated a lateralsemiconductor device containing a high mobility channel and aheterojunction which preferably coincides with the junction of sourceand/or drain, it will be apparent to those skilled in the art thatmodifications and variations are possible without deviating from thebroad scope of the invention which shall be limited solely by the scopeof the claims appended hereto.

1. A method of preparing a lateral strained silicon channel for a fieldeffect transistor comprising the steps of (FIG. 4): providing asubstrate having a relaxed Si_(1-z)Ge_(z) epitaxial region 81 and dopingregion 81 p-type, forming spaced apart strained silicon regions 82 and83 within said relaxed Si_(1-z)Ge_(z) region 81, doping said strainedsilicon regions 82 and 83 n-type to a concentration level greater than1×10¹⁹ atoms/cm³, and forming a strained silicon region 84 over saidrelaxed Si_(1-z)Ge_(z) region 81 which is situated between said strainedsilicon regions 82 and
 83. 2. The method of claim 1 further includingthe steps of forming a gate dielectric region 85 over the above strainedsilicon region 84, and forming a conducting region 86 over said gatedielectric region
 85. 3. The method of claim 2 further including thestep of forming a gate stack 111 comprising both said gate dielectricregion 85 and said conducting region 86, which overlaps said relaxedSi_(1-z)Ge_(z) region 81 between said strained silicon regions 82 and83.
 4. The method according to claim 3 wherein said gate stackcomprising said gate dielectric region 85 and conducting region 86 isself-aligned with respect to said spaced apart strained silicon regions82 and
 83. 5. The method according to claim 1 wherein prior to said stepof providing a relaxed Si_(1-z)Ge_(z) epitaxial region 81 performing thestep of forming a Si_(1-x)Ge_(x) epitaxial layer
 94. 6. The methodaccording to claim 5 wherein said Si_(1-x)Ge_(x) epitaxial region 94 isformed having a germanium profile content selected from the groupconsisting of a linear graded germanium content x, a step gradedgermanium content x and a uniform content x.
 7. The method according toclaim 1 wherein said relaxed Si_(1-z)Ge_(z) epitaxial region 81 is dopedp-type by a process selected from the group consisting of ionimplantation followed by annealing and in situ doping.
 8. The methodaccording to claim 1 wherein said strained silicon layers 82 and 83 arestrained with respect to said Si_(1-z)Ge_(z) layer 81, and doped n-typeby a process selected from the group consisting of ion implantation andin situ doping.
 9. The method according to claim 1 wherein said gatedielectric layer 85 is selected from the group consisting of oxide,nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr,La, Y, Ta, singly or in combination.
 10. The method according to claim 1wherein said dielectric regions 87 and 88 are selected from the groupconsisting of an oxide, nitride, oxynitride, and a dielectric materialwith a permittivity below
 4. 11. The method according to claim 2 whereinsaid conducting region 86 is selected from the group consisting of ametal, metal silicide, a doped poly silicon, or doped poly SiGe.
 12. Themethod according to claim 1 wherein the strained silicon region 84 isauto doped n-type in the area next to the n-type strained siliconregions 82 and 83, and auto doped p-type in the area next to the p-typeepitaxial region Si_(1-z)Ge_(z)
 81. 13. The method according to claim 1wherein the strained silicon layer 84 is grown after a chemicalmechanical polishing (CMP) of the upper surface of said body
 81. 14. Amethod of preparing a lateral channel for a field effect transistorcomprising the steps of (FIG. 5): providing a substrate having a singlecrystal silicon region 31 doped p-type, forming spaced apart strainedSi_(1-y)C_(y) epitaxial region 32 and 33 within said p-type siliconlayer 31, doping said strained Si_(1-y)C_(y) regions 32 and 33 n-type toa concentration level greater than 1×10¹⁹ cm⁻³, and forming a siliconregion 34 over said n-type strained Si_(1-y)C_(y) epitaxial regions 32and 33, and p-type silicon 31 there between.
 15. The method of claim 14further comprising the steps of: forming a gate dielectric region 35over said silicon region 34, and forming a conducting region 36 over theabove gate dielectric layer
 35. 16. The method of claim 15 futherincluding the steps of forming a gate stack 888 comprising both saiddielectric layer 35 and said conducting region 36, which overlaps saidsilicon 31 between said strained Si_(1-y)C_(y) regions 32 and
 33. 17.The method according to claim 16 further comprising the steps of:forming a blanket dielectric layer 37 over and above said gate stack888, forming a dielectric layer 38 on the sidewall of said gate stack888′, forming a blanket dielectric layer 39 over the entire structure,forming a conducting via 40 through the above blanket dielectric layer39 in contact to said silicon region 34 in the region on top of then-type region 33, forming a conducting via 42 through the above blanketdielectric layer 39 in contact to said silicon region 34 in the regionon top of said n-type region 32, and forming a conducting via 41 throughthe above blanket dielectric layer 39 in contact to said conductingregion 36 at the top of said gate stack.
 18. The method according toclaim 14 wherein said strained Si_(1-y)C_(y) layers 32, 33 are formed bya process selected from the group consisting of CVD, MBE, and carbonimplantion into silicon followed by recrystalization.
 19. The methodaccording to claim 14 wherein said silicon region 31 is doped p-type bya process selected from the group consisting of ion implantationfollowed by annealing, and in situ doping during epitaxial growth by CVDor MBE.
 20. The method according to claim 15 wherein said gatedielectric region 35 is selected from the group consisting of an oxide,nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr,La, Y, Ta, singly or in combination.
 21. The method according to claim17 wherein said gate dielectric region 37 is selected from the groupconsisting of an oxide, nitride, oxynitride of silicon, and oxides andsilicates of Hf, Al, Zr, La, Y, Ta, singly or in combination.
 22. Themethod according to claim 14 wherein said strained Si_(1-y)C_(y) regions32 and 33 are doped n-type by a process selected from the groupconsisting of ion implantation followed by annealing and in situ dopingduring epitaxial growth by CVD or MBE.
 23. The method according to claim17 wherein said dielectric region 38 is selected from the groupconsisting of an oxide, nitride, oxynitride, and a dielectric materialwith a permittivity below
 4. 24. The method according to claim 15wherein said conducting region 36 is selected from the group consistingof metal, metal silicide, a doped poly silicon and a doped poly SiGe.25. The method according to claim 14 wherein said silicon region 34 isauto doped n-type in the area next to the n-type strained Si_(1-y)C_(y)regions 32 and 33, and auto doped p-type in the area next to said p-typesilicon region 31 after annealing.
 26. The method according to claim 14wherein the auto doping in said silicon region 34 and the activation ofsaid dopants in said doped regions are performed by a process selectedfrom the group consisting of rapid thermal annealing, furnace annealingand laser annealing.
 27. The method according to claim 14 wherein adielectric region 50 is formed by a process selected from the groupconsisting of shallow trench isolation (STI) and local oxidation ofsilicon (LOCAS).
 28. The method according to claim 14 wherein saidsilicon region 34 is formed after a step of chemical mechanicalpolishing (CMP).
 29. A method of preparing an inverter made of lateralchannel field effect transistors comprising the steps of (FIG. 6):forming a first transistor comprising the steps of: forming a siliconlayer 31 on a first single crystalline substrate 30, doping said siliconlayer 31 p-type, forming a strained Si_(1-y)C_(y) epitaxial region 32and 33 over said p-type silicon layer 31, doping the above strainedSi_(1-y)C_(y) layer 32, 33 n-type to a concentration level greater than1E19 cm⁻³, forming a thin silicon layer 34 over the above n-typestrained Si_(1-y)C_(y) epitaxial layer 32, 33, and p-type silicon 31,forming a dielectric layer 50 serving as device isolation, forming athin dielectric layer 35 over the above silicon layer 34, forming aconducting layer 36 over the above dielectric layer 35, forming a gatestack 888 comprising both the above dielectric layer 35 and theconducting layer 36, which overlaps the silicon 31 and the part of thestrained Si_(1-y)C_(y) 32, 33, forming a blanket dielectric layer 37over and above the gate stack 888, forming a dielectric layer 38 on thesidewall of the gate stack 888, forming a second transistor comprisingthe steps of: forming a silicon layer 131 on a first single crystallinesubstrate 30, doping said silicon layer 131 n-type, forming acompressively strained Si_(1-x)Ge_(x) epitaxial region 132 and 133 insaid p-type silicon layer 31, doping the above strained Si_(1-x)Ge_(x)layer 132 and 133 p-type to a concentration level greater than 1E19cm⁻³, forming a thin silicon or a compressively strained Si_(1-w)Ge_(w)layer 134 over the above p-type strained Si_(1-x)Ge_(x) epitaxial layer132, 133 and n-type silicon 131, forming a thin dielectric layer 135over the above layer 134, and forming a conducting layer 136 over theabove dielectric layer 135, forming a gate stack comprising both theabove dielectric layer 135 and the conducting layer 136, which overlapsthe silicon 131 and part of region 132,
 133. 30. The method according toclaim 29 further comprising the steps of: forming a blanket dielectriclayer 137 over and above the gate stack 666, forming a dielectric layer138 on the sidewall of the gate stack 666′, forming a blanket dielectriclayer 39 over the entire structure, forming a conducting layer 40through the above blanket dielectric layer 39 in contact to the siliconlayer 34 in the region on top of the n-type 33, forming a conductinglayer 42 through the above blanket dielectric layer 39 in contact to thesilicon layer 34 in the region on top of the n-type 32, forming aconducting layer 41 through the above blanket dielectric layer 39 and 37in contact to the conducting layer 36 at the top of the gate stack 888,forming a conducting layer 142 through the above blanket dielectriclayer 39 in contact to layer 134 in the region on top of the n-typelayer 133, forming a conducting layer 140 through the above blanketdielectric layer 39 in contact to layer 134 in the region on top of then-type layer 132, forming a conducting layer 141 through the aboveblanket dielectric layer 39 and 137 in contact to the conducting layer136 at the top of the gate stack 666, and forming dielectric region 50on layer 30 or 30′ in between region 31 and 131 to serve as deviceisolation.
 31. The method according to claim 29 wherein substrate 30 canbe bulk silicon, or SOI.
 32. The method according to claim 29 whereinthe steps of forming said second transistor and performed before saidsteps of forming said first transistor.
 33. The method according toclaim 29 wherein prior to forming silicon layer 34, performing chemicalmechanical polishing (CMP).
 34. The method according to claim 29 whereinlayer 134 is grown after the step of chemical mechanical polishing(CMP).
 35. A method of preparing an inverter made of lateral channelfield effect transistors comprising the steps of (FIG. 7): forming afirst transistor comprising the steps of: forming a relaxed SiGe layer531 on a first single crystalline substrate 30, doping said SiGe layer531 p-type, forming a strained silicon epitaxial region 532 and 533 oversaid p-type SiGe layer 531, doping the above strained silicon layer 532,533 n-type to a concentration level greater than 1E19 cm⁻³, forming athin strained silicon layer 534 over the above n-type strained siliconepitaxial layer 532, 533, and p-type SiGe 531, forming a dielectriclayer 50 served as device isolation, forming a thin dielectric layer 35over the above silicon layer 534, forming a conducting layer 36 over theabove dielectric layer 35, forming a gate stack 888 comprising both theabove dielectric layer 35 and the conducting layer 36, which overlapsSiGe 531 and the part of the strained silicon region 532, 533, forming ablanket dielectric layer 37 over and above the gate stack 888, forming adielectric layer 38 on the sidewall of the gate stack 888′, forming asecond transistor comprising the steps of: forming a silicon layer 131on a first single crystalline substrate 30, doping said silicon layer131 n-type, forming a compressively strained Si_(1-x)Ge_(x) epitaxialregion 132 and 133 over said p-type silicon layer 131, doping the abovestrained Si_(1-x)Ge_(x) layer 132 and 133 p-type to a concentrationlevel greater than 1E19 cm⁻³, forming a thin silicon or a compressivelystrained Si_(1-w)Ge_(w) layer 134 over the above p-type strainedSi_(1-x)Ge_(x) epitaxial layer 132, 133 and n-type silicon 131, forminga thin dielectric layer 135 over the above layer 134, and forming aconducting layer 136 over the above dielectric layer 135, forming a gatestack comprising both the above dielectric layer 135 and the conductinglayer 136, which overlaps the silicon 131 and part of region 132, 133.36. A method according to claim 35 further comprising the steps of:forming a blanket dielectric layer 137 over and above the gate stack666, forming a dielectric layer 138 on the sidewall of the gate stack666′, forming a blanket dielectric layer 39 over the entire structure,forming a conducting layer 40 through the above blanket dielectric layer39 in contact to the silicon layer 534 in the region on top of then-type 533, forming a conducting layer 42 through the above blanketdielectric layer 39 in contact to the silicon layer 534 in the region ontop of the n-type 532, forming a conducting layer 41 through the aboveblanket dielectric layer 39 and 37 in contact to the conducting layer 36at the top of the gate stack 888, forming a conducting layer 142 throughthe above blanket dielectric layer 39 in contact to layer 134 in theregion on top of the n-type layer 133, forming a conducting layer 140through the above blanket dielectric layer 39 in contact to layer 134 inthe region on top of the n-type layer 132, forming a conducting layer141 through the above blanket dielectric layer 39 and 137 in contact tothe conducting layer 136 at the top of the gate stack 666, and formingdielectric region 50 on layer 30 in between region 531 and 131 to serveas device isolation.
 37. The method according to claim 35 whereinsubstrate 30 can be bulk silicon, relaxed SiGe, bulk Ge or SOI, or SGOIor GOI.
 38. The method according to claim 35 wherein the steps offorming said second transistor and performed before said steps offorming said first transistor.
 39. The method according to claim 35wherein prior to forming silicon layer 534, performing chemicalmechanical polishing (CMP).
 40. The method according to claim 35 whereinlayer 134 is grown after the step of chemical mechanical polishing(CMP).
 41. A field effect transistor comprising: a substrate having arelaxed Si_(1-z)Ge_(z) epitaxial region 81 doped p-type, spaced apartstrained silicon regions 82 and 83 within said relaxed Si_(1-z)Ge_(z)region 81, said strained silicon regions 82 and 83 doped n-type to aconcentration level greater than 1×10¹⁹ atoms/cm³, a strained siliconregion 84 over said relaxed Si_(1-z)Ge_(z) region 81 and said strainedsilicon regions 82 and 83, a gate dielectric region 85 over saidstrained silicon region 84, and a conducting region 86 over said gatedielectric region
 85. 42. The field effect transistor according to claim41 further including a gate stack 111 comprising both said gatedielectric region 85 and said conducting region 86, which overlaps saidrelaxed Si_(1-z)Ge_(z) region 81 between said strained silicon regions82 and
 83. 43. The field effect transistor according to claim 42 whereinsaid gate stack comprising said gate dielectric region 85 and conductingregion 86 is self-aligned with respect to said spaced apart strainedsilicon regions 82 and
 83. 44. The field effect transistor according toclaim 41 further including a Si_(1-x)Ge_(x) epitaxial layer 94 belowsaid relaxed Si_(1-z)Ge_(z) region
 81. 45. The field effect transistoraccording to claim 44 wherein said Si_(1-x)Ge_(x) epitaxial region 94has a germanium profile content selected from the group consisting of alinear graded germanium content x, a step graded germanium content x anda uniform content x.
 46. The field effect transistor according to claim41 wherein said gate dielectric layer 85 is selected from the groupconsisting of oxide, nitride, oxynitride of silicon, and oxides andsilicates of Hf, Al, Zr, La, Y, Ta, singly or in combination.
 47. Thefield effect transistor according to claim 41 wherein said dielectricregions 87 and 88 are selected from the group consisting of an oxide,nitride, oxynitride, and a dielectric material with a permittivity below4.
 48. The field effect transistor according to claim 42 wherein saidconducting region 86 is selected from the group consisting of a metal,metal silicide, a doped poly silicon, or doped poly SiGe.
 49. The fieldeffect transistor according to claim 41 wherein the strained siliconregion 84 is doped n-type in the area next to the n-type strainedsilicon regions 82 and 83, and doped p-type in the area next to thep-type epitaxial region Si_(1-z)Ge_(z)
 81. 50. The field effecttransistor according to claim 41 wherein said strained silicon layer 84is grown on a chemical mechanical polished (CMP) upper surface of saidbody
 81. 51. A field effect transistor comprising: a substrate having asingle crystal silicon region 31 doped p-type, spaced apart strainedSi_(1-y)C_(y) epitaxial region 32 and 33 within said p-type siliconlayer 31, said strained Si_(1-y)C_(y) regions 32 and 33 doped n-type toa concentration level greater than 1×10¹⁹ cm⁻³, a silicon region 34 oversaid n-type strained Si_(1-y)C_(y) epitaxial regions 32 and 33, andp-type silicon 31 there between, a gate dielectric region 35 over saidsilicon region 34, and a conducting region 36 over the above gatedielectric layer
 35. 52. The field effect transistor of claim 51 futherincluding a gate stack 888 comprising both said dielectric layer 35 andsaid conducting region 36, which overlaps said silicon 31 between saidstrained Si_(1-y)C_(y) regions 32 and
 33. 53. The field effecttransistor according to claim 52 further comprising: a blanketdielectric layer 37 over and above said gate stack 888, a dielectriclayer 38 on the sidewall of said gate stack 888′, a blanket dielectriclayer 39 over the entire structure, a conducting via 40 through theabove blanket dielectric layer 39 in contact to said silicon region 34in the region on top of the n-type region 33, a conducting via 42through the above blanket dielectric layer 39 in contact to said siliconregion 34 in the region on top of said n-type region 32, and aconducting via 41 through the above blanket dielectric layer 39 incontact to said conducting region 36 at the top of said gate stack. 54.The field effect transistor according to claim 51 wherein said gatedielectric region 35 is selected from the group consisting of an oxide,nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr,La, Y, Ta, singly or in combination.
 55. The field effect transistoraccording to claim 51 wherein said gate dielectric region 37 is selectedfrom the group consisting of an oxide, nitride, oxynitride of silicon,and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or incombination.
 56. The field effect transistor according to claim 53wherein said dielectric region 38 is selected from the group consistingof an oxide, nitride, oxynitride, and a dielectric material with apermittivity below
 4. 57. The field effect transistor according to claim52 wherein said conducting region 36 is selected from the groupconsisting of metal, metal silicide, a doped poly silicon and a dopedpoly SiGe.
 58. The field effect transistor according to claim 51 whereinsaid silicon region 34 is doped n-type in the area next to the n-typestrained Si_(1-y)C_(y) regions 32 and 33, and doped p-type in the areanext to said p-type silicon region
 31. 59. The field effect transistoraccording to claim 51 wherein said silicon region 34 is formed on achemical mechanical polished (CMP) substrate
 31. 60. An inverter made oflateral channel field effect transistors comprising: a first transistorcomprising: a silicon layer 31 on a first single crystalline substrate30, said silicon layer 31 doped p-type, a strained Si_(1-y)C_(y)epitaxial region 32 and 33 in said p-type silicon layer 31, the abovestrained Si_(1-y)C_(y) layer 32, 33 doped n-type to a concentrationlevel greater than 1E19 cm⁻³, a thin silicon layer 34 over the aboven-type strained Si_(1-y)C_(y) epitaxial layer 32, 33, and p-type silicon31, a dielectric layer 50 to provide device isolation, a gate dielectriclayer 35 over said silicon layer 34, a conducting layer 36 over saiddielectric layer 35, a gate stack 888 comprising both the abovedielectric layer 35 and the conducting layer 36, which overlaps thesilicon 31 and the part of the strained Si_(1-y)C_(y) 32, 33, a blanketdielectric layer 37 over and above the gate stack 888, a dielectriclayer 38 on the sidewall of the gate stack 888′, a second transistorcomprising: a silicon layer 131 on a first single crystalline substrate30, said silicon layer 131 doped n-type, a compressively strainedSi_(1-x)Ge_(x) epitaxial region 132 and 133 in said n-type silicon layer131, the above strained Si_(1-x)Ge_(x) layer 132 and 133 doped p-type toa concentration level greater than 1E19 cm⁻³, a thin silicon or acompressively strained Si_(1-w)Ge_(x) layer 134 over the above p-typestrained Si_(1-x)Ge_(x) epitaxial layer 132, 133 and n-type silicon 131,a gate dielectric layer 135 over said layer 134, a conducting layer 136over said gate dielectric layer 135, and a gate stack comprising bothsaid dielectric layer 135 and said conducting layer 136, which overlapsthe silicon 131 and part of region 132,
 133. 61. The inverter accordingto claim 60 further comprising: a blanket dielectric layer 137 over andabove the gate stack 666, a dielectric layer 138 on the sidewall of thegate stack 666′, a blanket dielectric layer 39 over the entirestructure, a conducting layer 40 through the above blanket dielectriclayer 39 in contact to the silicon layer 34 in the region on top of then-type 33, a conducting layer 42 through the above blanket dielectriclayer 39 in contact to the silicon layer 34 in the region on top of then-type 32, a conducting layer 41 through the above blanket dielectriclayer 39 and 37 in contact to the conducting layer 36 at the top of thegate stack 888, a conducting layer 142 through the above blanketdielectric layer 39 in contact to layer 134 in the region on top of then-type layer 133, a conducting layer 140 through the above blanketdielectric layer 39 in contact to layer 134 in the region on top of then-type layer 132, a conducting layer 141 through the above blanketdielectric layer 39 and 137 in contact to the conducting layer 136 atthe top of the gate stack 666, and a dielectric region 50 on layer 30 or30′ in between region 31 and 131 to provide device isolation.
 62. Theinverter according to claim 60 wherein said substrate 30 is selectedfrom the group consisting of bulk silicon, SOI, SOS and SGOI.
 63. Theinverter according to claim 60 wherein said silicon layer 34, is formedon a chemical mechanical polished (CMP) surface.
 64. The inverteraccording to claim 60 wherein said layer 134 is formed on a chemicalmechanical polished (CMP) surface.
 65. An inverter made of lateralchannel field effect transistors comprising: a first transistorcomprising: a relaxed SiGe layer 531 on a first single crystallinesubstrate 30, said SiGe layer 531 doped p-type, a strained siliconepitaxial region 532 and 533 in said p-type SiGe layer 531, the abovestrained silicon layer 532, 533 doped n-type to a concentration levelgreater than 1E19 cm⁻³, a thin strained silicon layer 534 over the aboven-type strained silicon epitaxial layer 532, 533, and p-type SiGe 531, adielectric layer 50 to provide device isolation, a gate dielectric layer35 over the above silicon layer 534, a conducting layer 36 over theabove dielectric layer 35, a gate stack 888 comprising both the abovedielectric layer 35 and the conducting layer 36, which overlaps SiGe 531and the part of the strained silicon region 532, 533, a blanketdielectric layer 37 over and above the gate stack 888, a dielectriclayer 38 on the sidewall of the gate stack 888′, a second transistorcomprising: a silicon layer 131 on a first single crystalline substrate30, said silicon layer 131 doped n-type, a compressively strainedSi_(1-x)Ge_(x) epitaxial region 132 and 133 in said p-type silicon layer131, the above strained Si_(1-x)Ge_(x) layer 132 and 133 doped p-type toa concentration level greater than 1E19 cm⁻³, a thin silicon or acompressively strained Si_(1-w)Ge_(w) layer 134 over said n-typestrained Si_(1-x)Ge_(x) epitaxial layer 132, 133 and p-type silicon 131,a gate dielectric layer 135 over said layer 134, a conducting layer 136over said dielectric layer 135, and a gate stack comprising both theabove dielectric layer 135 and the conducting layer 136, which overlapsthe silicon 131 and part of region 132,
 133. 66. The inverter accordingto claim 65 further comprising: a blanket dielectric layer 137 over andabove the gate stack 666, a dielectric layer 138 on the sidewall of thegate stack 666′, a blanket dielectric layer 39 over the entirestructure, a conducting layer 40 through the above blanket dielectriclayer 39 in contact to the silicon layer 534 in the region on top of then-type 533, a conducting layer 42 through the above blanket dielectriclayer 39 in contact to the silicon layer 534 in the region on top of then-type 532, a conducting layer 41 through the above blanket dielectriclayer 39 and 37 in contact to the conducting layer 36 at the top of thegate stack 888, a conducting layer 142 through the above blanketdielectric layer 39 in contact to layer 134 in the region on top of then-type layer 133, a conducting layer 140 through the above blanketdielectric layer 39 in contact to layer 134 in the region on top of then-type layer 132, a conducting layer 141 through the above blanketdielectric layer 39 and 137 in contact to the conducting layer 136 atthe top of the gate stack 666, and a dielectric region 50 on layer 30 inbetween region 531 and 131 to provide device isolation.
 67. The inverteraccording to claim 65 wherein said substrate 30 is selected from thegroup consisting of bulk silicon, relaxed SiGe, bulk Ge, SOI, SGOI, SOSand GOI.
 68. The inverter according to claim 65 wherein said siliconlayer 534 is formed on a chemical mechanical polished (CMP) surface. 69.The inverter according to claim 65 wherein layer 134 is formed on achemical mechanical polished (CMP) surface.